Typical memory systems use either an asynchronous or synchronous clocking scheme to transmit data between the memory controller and the memory device. Synchronous clocking means that the memory device waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus. Synchronous dynamic random access memory (SDRAM) is widely used since such devices typically support higher clock speeds than asynchronous memory devices.
Double data rate (DDR) SDRAM transfers data on both the rising and falling edges of the clock signal. Such memory devices use a lower clock frequency but require strict control of the timing of the electrical data and clock signals. The first version of such devices (DDR1) achieved nearly twice the bandwidth of a single data rate (SDR) SDRAM running at the same clock frequency. DDR2 and DDR3 SDRAM devices are subsequent improvements over DDR1 devices. Regardless of which type of memory is used, a physical interface (Phy) is coupled directly between the memory controller and the memory devices. The Phy interface generally includes circuitry for handling the timing requirements of the data, command, address and associated strobes. For example, Phy may include delay circuitry configured to properly locate the data strobe in the data eye.
Data transferred between memory and a processor, or vice versa, over real channels (wires/transmission lines) severely degrades the receive data eye. In particular the channel characteristics introduces moderate to severe ISI (Inter Symbol Interference) for multi-gigabit ranges. The use of decision feedback equalization (DFE) may help in properly receiving these degraded eyes. However, current designs are not optimized to receive data just after the read preamble.